1. Field of the Invention
The present invention relates to test and measurement of signals and circuits.
2. Description of Related Art
Propagation delays and transition times of signals in integrated circuits (ICs) are targets of many specifications and tests. As these delays and times continue to decrease to the picosecond realm, measuring them is more difficult due to limits of physics, and accuracy is more important because inaccuracy can greatly affect test yield.
Rise and fall times are typically specified as shown in FIG. 1 at specific voltage thresholds, and for very high speed data signals, the duration relative to the bit duration or unit interval (UI) is most important.
Circuits for measuring signal transitions at specific voltage thresholds typically involve two comparators, but it is also possible to use a single comparator and to adjust the threshold voltage, though this can change the delay through the comparator. Alternatively, the signal can be AC-coupled to the comparator and the signal's bias voltage changed relative to a constant comparator reference voltage as shown in FIG. 2A and FIG. 2B.
Applicant's U.S. patent application Ser. No. 10/947,189 filed on Sep. 23, 2004 for “Circuit and method for Measuring Jitter of High Speed Signals”, incorporated herein by reference, describes and claims a circuit and method for measuring jitter in high speed digital signals wherein the signal is coherently undersampled by a latching circuit 10 clocked at a frequency that is not an integer ratio of the data rate, as shown in FIG. 3. The output signal of the latching circuit will contain unstable bits caused by jitter in the undersampled data signal. The sampling resolution as a percent of the sampled signal period is the percent offset of the sampling clock frequency (relative to an integer ratio with the sampled signal frequency). The aforementioned application also describes a median detector circuit, whose schematic, state diagram, and waveforms are shown in FIG. 4, incorporated in analysis circuit 12 (FIG. 3A) that detects the median time in a sequence of unstable bits caused by sampling a jittered signal. The application also describes how the invention could be connected to a serializer/deserializer (SerDes) circuit 14, as shown in FIG. 5, to deduce an aspect of jitter tolerance by undersampling and measuring the pulse width or duty cycle of the logical OR of the input and output signals of a clock-data recovery (CDR) circuit 16.
In a 2001 VLSI Test Symposium paper entitled, “An On-chip Short-Time Interval Measurement Technique for testing High-Speed Communication Links”, J-L Huang and K-T Cheng describe a technique for measuring delays by using coherent undersampling and counting the number of sampling clock cycles from the transition of one signal's samples to the transition of the delayed signal's samples. The transitions are required to be from continuous 0's to continuous 1's, or vice versa. To ensure that, the technique requires the signal to have the RMS jitter less than or equal to 15% of the sampling resolution to ensure that measurement errors (“misfires”) will occur in less than one per million tests. The sampling resolution equals T/N, where T is the period of the sampled signal, and N is the minimum number of sampling clock periods that equals an integer multiplied by T. Therefore, for 1 picosecond RMS jitter in the sampling clock or the signal being measured, the sampling resolution needs to be larger than 6 picoseconds.
Other prior art delay measurement circuits and methods have included calibrated delay lines, a ring oscillator (Applicant's U.S. Pat. No. 5,923,676, for “BIST Architecture for Measurement of Integrated Circuit Delays”), or a tuned pair of ring oscillators (Frisch et. al. U.S. Pat. No. 6,295,315, for “Jitter Measurement System and Method”). The measurement accuracy of these circuits is limited by jitter in the signals being measured or by jitter in the measurement circuitry itself, and by the basic resolution (minimum delay step in the measurement circuitry). The best reported basic resolution is a few picoseconds, but this resolution is typically overwhelmed by the measurement circuit's self-jitter (typically more than 10 picoseconds RMS for built-in self-test circuitry, and typically more than 2 picoseconds RMS for external test circuitry). Each of these various techniques can measure only one delay at a time.
Some prior art circuit and methods measure delays and transition times of an IC's input/output (I/O) pins. Applicant's U.S. Pat. No. 6,586,921, for “Method and Circuit for Testing DC Parameters of Circuit Input and Output Nodes”, describes a technique that measures I/O pin delays that are longer than a few clock periods and caused by leakage currents across intrinsic node capacitance or caused by drive currents across intentionally-added external capacitance. Aforementioned U.S. Pat. No. 5,923,676 describes a delay measurement circuit that can be used to measure I/O pin delays. In a 1998 International Test Conference paper entitled, “Delay Test of Chip I/Os Using LSSD Boundary Scan” Gillis et. al. describe a technique in which an external tester accurately applies a launch pulse on one clock input pin and applies a capture pulse on another clock input pin of the IC under test, and by adjusting the interval between the two pulses can deduce the path delay between the IC's launching register output and the capturing register input. Special circuitry is added to on-chip boundary scan circuitry at each I/O pin of the IC. All of these prior art techniques can measure the delay of only one pin at a time.